1 Rupee ST, Pune [July 2019]  - [Oct 2019]

RTL Design Trainee

• Swayambhu Processor design using FPGA

• RTL design and verification for peripherals as RISC Pipelined Controller, Asynchronous Hardware FIFO, Communication Interfaces as SDRAM Controller, UART, and I2C

• Detailed design Study of ALU, Magnitude comparator, Single port RAM, Gray counters, ADC/DAC & FSM

• Hardware: Spartan XC3S500E, Virtex5

• Tools: Xilinx ISE 14.7 (Verilog)

Tata Consultancy Services, Mumbai [Feb 2021]  - [July 2021]

Analyst at Data Platforms, Data Intelligence & Analytics Group

• Deputed to Banking Client for Business Analyst work

• Experienced different stages of Data Science Project Lifecycle

• Explored various areas of Machine Learning  

• Skills: R, SAS, SQL

AERONAUTICAL DEVELOPEMENT AGENCY, Ministry of Defence (Govt of India) [Aug 2021]  - [July 2022]

Project Assistant / Research Fellow

• UNDISCLOSED DUTIES

• Area of Expertise: Applied R&D, Design/Modelling & Simulation, Performance Evaluation/Testing & Quality assurance

• Avionics Standards: RS232/422, RS485, MIL-STD-1553B, DO-178B